#-------------------------
# compile
#-------------------------
compile

#change_names
#change_names -rules verilog -verbose -hier
#-------------------------
# check
#-------------------------
check_timing > ${log}/${top_design}_uncon_path.log
check_design > ${log}/${top_design}_check.log

#-------------------------
# save the design
#-------------------------
write_file -f verilog -hierarchy -output ${out}/${top_design}_mapped.v
write_file -f ddc     -hierarchy -output ${out}/${top_design}_mapped.ddc
write_sdf ${out}/${top_design}.sdf
write_sdc ${out}/${top_design}.sdc
write_script -format dctcl -hierarchy -output ${run}/${top_design}.tcl


#-------------------------
# report
#-------------------------
proc cal_freq { clock_period } {
  return [expr 1000/$clock_period];
}
report_clock -skew > ${log}/${top_design}_clk.log
echo "The frequency of the design is :" >> ${log}/${top_design}_clk.log
echo "-----------------------------" >> ${log}/${top_design}_clk.log
echo [cal_freq $clk_period] "MHz" >> ${log}/${top_design}_clk.log
echo "-----------------------------" >> ${log}/${top_design}_clk.log

report_timing > ${log}/${top_design}_timing.log
report_constraints -all_violators > ${log}/${top_design}_con.log
report_reference > ${log}/${top_design}_reference.log
report_area > ${log}/${top_design}_area.log
report_power > ${log}/${top_design}_power.log
report_port > ${log}/${top_design}_port.log

report_lib typical > ${out}/use_lib.message

#-------------------------
# exit
#---------------------
